Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors

Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challenging to implement in future high-performance processors. In particular, the the original Perceptron branch predictor suffers from a long access latency, and the faster path-based neural predictor (PBNP) requires deep pipelining and additional area to support checkpointing for misprediction recovery. The complexity of the PBNP predictor stems from the fact that the path history length, which determines the number of tables and pipeline stages, is equal to the history length, which is typically very long for high accuracy. We propose to decouple the path-history length from the outcomehistory length through a new technique called modulo-path history. By allowing a shorter path history, we can implement a PBNP with significantly fewer tables and pipeline stages while still exploiting a traditional long branch ...

• Type: Conference
• Year: 2006
• Where: sbacpad
• Authors: Daniel A. Jiménez, Gabriel H. Loh
• Keywords: Branch Predictor, Computer Architecture, Hardware, Path History Length, Pipeline Stages, SBACPAD 2006