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21

GLVLSI
1999
IEEE

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A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability

14 years 4 months ago

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability

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Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agraw

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Added	03 Aug 2010
Updated	03 Aug 2010
Type	Conference
Year	1999
Where	GLVLSI
Authors	Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal

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