Criticality-based optimizations for efficient load processing

Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Previous work has shown that the criticality of instructions can be dynamically predicted with high accuracy, and that this information can be leveraged to optimize the performance of load value prediction and instruction steering for clustered architectures. In this work, we revisit the idea of criticality, but we propose several processor enhancements that can exploit criticality information and can be directly applied to modern x86 microarchitectures. For the investment of a small (less than 1KB) criticality predictor, we can make a conventional single-read-port data cache achieve the performance of an ideal dual-read-port cache, yielding an average 10% performance improvement. Our remaining techniques can reuse the predictor (i.e., no additional overhead) to further optimize other aspects of load processing...

• Type: Conference
• Year: 2009
• Where: HPCA
• Authors: Samantika Subramaniam, Anne Bracy, Hong Wang 0003, Gabriel H. Loh
• Keywords: Average 10% Performance, Computer Architecture, Criticality Predictor, HPCA 2009, Overall Performance Improvement