Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices

The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory system, the memory bus and DRAM devices run at the same data rate. To improve memory bandwidth, we propose a new memory system design called decoupled DIMM that allows the memory bus to operate at a data rate much higher than that of the DRAM devices. In the design, a synchronization buffer is added to relay data between the slow DRAM devices and the fast memory bus; and memory access scheduling is revised to avoid access conflicts on memory ranks. The design not only improves memory bandwidth beyond what can be supported by current memory devices, but also improves reliability, power efficiency, and cost effectiveness by using relatively slow memory devices. The idea of decoupling, precisely the decoupling of bandwidth match between memory bus and a single rank of devices, can also be applied to other ty...

• Type: Conference
• Year: 2009
• Where: ISCA
• Authors: Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
• Keywords: Data Rate, Hardware, ISCA 2009, Memory Bus, Memory Systems