Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture

Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architectures has shown that the design of buffers in the NoC routers influences the power consumption, area overhead and performance of the entire network. In this paper, we propose a low-power area-efficient NoC architecture by reducing the number of router buffers. As a reduction in the number of buffers degrades the network's performance, we propose to use the existing repeaters along the inter-router links as adaptive channel buffers for storing data when required. We evaluate the proposed adaptive communication channel buffers under static and dynamic buffer allocation in 8

• Type: Conference
• Year: 2007
• Where: ANCS
• Authors: Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
• Keywords: Adaptive Channel Buffers, ANCS 2007, Buffer Allocation, Channel Buffers, Computer Networks