Design and Analysis of LDPC Decoders for Software Defined Radio

Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.

• Type: Conference
• Year: 2007
• Where: SIPS
• Authors: Sangwon Seo, Trevor N. Mudge, Yuming Zhu, Chaitali Chakrabarti
• Keywords: LDPC Decoder, Scalable Ldpc Decoder, SIPS 2007, Wireless Standards