Design and analysis of matching circuit architectures for a closest match lookup

— This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny
• Keywords: Distributed And Parallel Computing, IPPS 2006, Search Trie, Value Match Lookup, Various Networking Lookup