Design and Evaluation of a Compiler Algorithm for Prefetching

Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefetching is useful in hiding the latency, issuing prefetches incurs an instruction overhead and can increase the load on the memory subsystem. As a result, care must be taken to ensure that such overheads do not exceed the benefits. This paper proposes a compiler algorithm to insert prefetch instructions into code that operates on dense matrices. Our algorithm identifies those references that are likely to be cache misses, and issues prefetches only for them. We have implemented our algorithm in the SUIF (Stanford University Intermediate Form) optimizing compiler. By generating fully functional code, we have been able to measure not only the improvements in cache miss rates, but also the overall performance of a simulated system. We show that our algorithm significantly improves the execution speed of our benchm...

• Type: Conference
• Year: 1992
• Where: ASPLOS
• Authors: Todd C. Mowry, Monica S. Lam, Anoop Gupta
• Keywords: Algorithm, ASPLOS 1992, Cache Misses, Memory Subsystem, Programming Languages