Design and Power Analysis in SysteC of an I2C Bus Driver

The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the execution of each system level instruction, stored in a Look-up Table, is used in a System level simulation. The methodology has been applied to the design of an I2 C bus driver

• Type: Conference
• Year: 2003
• Where: FDL
• Authors: Marco Caldari, Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti
• Keywords: FDL 2003, Level Functional Description, Level Instruction, System Level Simulation