Design Methodologies and Architecture Solutions for High-Performance Interconnects

In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. For technologies of 0.25µm and below, wiring capacitance dominates gate capacitance, thus rapidly increasing the interconnect-induced delay. Moreover, the coupling capacitance becomes a significant portion of the on-chip total wiring capacitance, and coupling between adjacent wires cannot be considered as a second-order effect any longer. As a consequence, the traditional top-down design methodology is ineffective, since the actual wiring delays can be computed only after layout parasitic extraction, when the physical design is completed. Fixing all the timing violations often requires several time-consuming iterations of logical and physical design, and it is essentially a trial-and-error approach. Increasingly tighter time-to-market requirements dictate that interconnect parasitics must be taken into accoun...

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Davide Pandini, Cristiano Forzan, Livio Baldi
• Keywords: Coupling Capacitance, Dominates Gate Capacitance, Hardware, ICCD 2004, Total Wiring Capacitance