Design of ultra high-speed CMOS CML buffers and latches

Abstract - A comprehensive study of ultra high-speed currentmode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, a new 20GHz regenerative latch circuit will be introduced. Experimental results show a higher performance for the new latch architecture compared to a conventional CML latch circuit at ultra high-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Payam Heydari, Ravindran Mohanavelu
• Keywords: Cml Buffers, ISCAS 2003, Latch Circuit, Regenerative Cml Latches