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IOLTS
2009
IEEE

Designing fault tolerant FSM by nano-PLA

14 years 6 months ago
Designing fault tolerant FSM by nano-PLA
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area overhead and the number of crosspoint devices are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The suggested scheme provides significant reduction of the area overhead without increasing of a number of crosspoint devices in comparison with known solutions. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides a number of trade-offs between the area and the number of devices in designing FSMs by PLAs. Benchmark based estimations of overheads demonstrate significant improvements of known fault tolerant techniques by using the newly proposed method.
Samary Baranov, Ilya Levin, Osnat Keren, Mark G. K
Added 24 May 2010
Updated 24 May 2010
Type Conference
Year 2009
Where IOLTS
Authors Samary Baranov, Ilya Levin, Osnat Keren, Mark G. Karpovsky
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