Deterministic Parallel Processing

Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, containing several hundred heterogeneous processors, connected through a novel, compile-time scheduled interconnect. This architecture does not suffer from many of the problems faced by conventional general purpose parallel processors and provides an alternative to creating an ASIC. The PC102 is the second generation device from picoChip containing 308 processors. The devices are designed to be connected together using a seamless extension of the internal interconnect structure. This enables multi-chip solutions to be easily realised for applications which require additional processing. This paper highlights some of the difficulties encountered when building parallel systems and goes on to show how the features of the picoArrayTM allow deterministic processing to be achieved, how the tool chain allows programmi...

• Type: Journal
• Year: 2006
• Where: IJPP
• Authors: Gajinder Panesar, Daniel Towner, Andrew Duller, Alan Gray, Will Robbins
• Keywords: Compile-time Scheduled Interconnect, IJPP 2006, Internal Interconnect Structure, Processors