Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window

Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thread performance is not addressed. In this paper, we propose a new execution paradigm that utilizes multi-cores on a single chip collaboratively to achieve high performance for single-thread memoryintensive workloads while maintaining the flexibility to support multithreaded applications. The proposed execution paradigm, dual-core execution, consists of two superscalar cores (a front and back processor) coupled with a queue. The front processor fetches and preprocesses instruction streams and retires processed instructions into the queue for the back processor to consume. The front processor executes instructions as usual except for cache-missing loads, which produce an invalid value instead of blocking the pipeline. As a result, the front processor runs far ahead to warm up the data caches and fix branch misp...

• Type: Conference
• Year: 2005
• Where: IEEEPACT
• Authors: Huiyang Zhou
• Keywords: Execution Paradigm, Hardware, IEEEPACT 2005, Multi-core Processors, Single-thread