Dynamic Branch Prediction for a VLIW Processor

This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and in the case of taken prediction it also predicts the issue-slot that contains the taken branch. This information is used to perform the BTB lookup. We compare this method against a typical superscalar branchpredictor and against a branchpredictor developedfor VLIWsby Intel and HP, For a 2K entry BHT, 512 entry BTB, gshare branchpredictor we obtain a nextpc misprediction rate of 7.83%. while a traditionalsuperscalar-type branchpredictor of comparable costs achieves 10.3% and the IntellHP predictor achieves 9.31%. In addition, we propose to have both predicted and delayed branches in the ISA and let the compiler select which type to apply. Simulationsshowperformance improvements of 2-7%for benchmarks that are well-knownfor their high misprediction rates. Thispaper also contributes an experiment to determine whe...

• Type: Conference
• Year: 2000
• Where: IEEEPACT
• Authors: Jan Hoogerbrugge
• Keywords: Branch Target, BTB Lookup, Developed Branch Predictor, Distributed And Parallel Computing, IEEEPACT 2000