Dynamic Compaction in SAT-Based ATPG

SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essential fault detection conditions and to generate patterns which cover multiple faults. We complement this technique by a state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained for an industrial benchmark circuit suite show that the new method outperforms earlier static approaches by approximately 23%.

• Type: Conference
• Year: 2009
• Where: ATS
• Authors: Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
• Keywords: ATS 2009, Dynamic Compaction Procedure, Hardware, SAT-based ATPG, SAT-based Automatic Test