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DSD
2004
IEEE

Dynamic Filter Cache for Low Power Instruction Memory Hierarchy

14 years 4 months ago
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
Filter cache(FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from energy efficient FC. The absence of cacheable loops leads to performance degradation in such FC structures. Therefore, we propose a simple dynamic FC scheme, which detects the opportunity for use of the FC and enables (or disables) it dynamically. Thus providing (slightly reduced) energy savings at minimal performance degradation. A combination of the predictive filter cache with the above schemes reduces the performance and energy penalty. For the benchmarks simulated with 256 Byte FC,
Kugan Vivekanandarajah, Thambipillai Srikanthan, S
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DSD
Authors Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya
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