Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility

In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture with a binary translation mechanism, being totally transparent for the software designer. Besides ensuring software compatibility, the technique allows porting the same code for different machines tracking technological evolutions. The target processor is a Java machine able to execute Java bytecodes. Experimental results show that even code without any available parallelism can benefit from the proposed approach. Algorithms used in the embedded systems domain were accelerated 4.6 times in the mean, while spending 10.89 times less energy in the average. We present results regarding the impact of area and power, and compare the proposed approach with other Java machines, including a VLIW one. Categories and Subject Descriptors

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Antonio Carlos Schneider Beck, Luigi Carro
• Keywords: Binary Translation Mechanism, Combinational Logic, Computer Architecture, DAC 2005, Java Machines