Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors

This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages by having a processor automatically invalidate its local copy of a cache block before a conflicting access by another processor. Eliminating invalidation overhead is particularly important under sequential consistency, where the latency of invalidating outstanding copies can increase a program’s critical path. DSI is applicable to software, hardware, and hybrid coherence schemes. In this paper we evaluate DSI in the context of hardware directory-based write-invalidate coherence protocols. Our results show that DSI reduces execution time of a sequentially consistent full-map coherence protocol by as much as 41%. This is comparable to an implementation of weak consistency that uses a coalescing write-buffer to allow up to 16 outstanding requests for exclusive blocks. When used in conjunction with weak consi...

• Type: Conference
• Year: 1995
• Where: ISCA
• Authors: Alvin R. Lebeck, David A. Wood
• Keywords: Cache Coherence Overhead, Coherence Protocol, DSI Eliminates Invalidation, Hardware, ISCA 1995