The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks

C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community as highly useful and profitable optimizations for FPGA designs, but have yet to find their way into the commercial toolflows. To quantify the significance of these techniques on real world applications, we have handimplemented three computational benchmarks which are taken directly from real world applications: Rijndael/AES encryption, a Smith/Waterman sequence matcher, and a simplified Microprocessor core, targeted to Xilinx Virtex family FPGAs. The combined use of datapath placement and C-slow retiming offer a 110% to 150% increase in throughput, improves place and route times, while increasing area and latency.

• Type: Conference
• Year: 2002
• Where: FCCM
• Authors: Nicholas Weaver, John Wawrzynek
• Keywords: FCCM 2002, FPGA Synthesis Community, Real World Applications, Virtex Family Fpgas, VLSI