Efficient microarchitecture policies for accurately adapting to power constraints

In the past years Dynamic Voltage and Frequency Scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won’t be useful at all (when static power exceeds dynamic power). In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We will predict the processor power consumption at a basic block level, using the consumed power translated into tokens to select between different power-saving microarchitectural techniques. These techniques are orthogonal to DVFS so they can be simultaneously applied. We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently....

• Type: Conference
• Year: 2009
• Where: IPPS
• Authors: Juan M. Cebrian, Juan L. Aragón, José M. García, Pavlos Petoumenos, Stefanos Kaxiras
• Keywords: Distributed And Parallel Computing, IPPS 2009, Microarchitectural Techniques, Power-saving Microarchitectural Techniques, Predefined Power Budget