Efficient Pipelining of Nested Loops: Unroll-and-Squash

The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs into silicon. Since streaming data processing in DSP applications is typically described by loop constructs in a high-level language, loops are the most critical portions of the hardware description and special techniques are developed to optimally synthesize them. In this paper, we introduce a new method for mapping and pipelining nested loops efficiently into hardware. It achieves fine-grain parallelism even on strong intra- and inter-iteration data-dependent inner loops and, by sharing resources economically, improves performance at the expense of a small amount of additional area. We implemented the transformation within the Nimble Compiler environment and evaluated its performance on several signal-processing benchmarks. The method achieves up to 2x improvement in the area efficiency compared to the best...

• Type: Conference
• Year: 2002
• Where: IPPS
• Authors: Darin Petkov, Randolph E. Harr, Saman P. Amarasinghe
• Keywords: Current Custom Vlsi, Data-dependent Inner Loops, Distributed And Parallel Computing, IPPS 2002, Synthesis Technology Bstract