An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic

We propose an efficient reconfigurable parallel prefix counting network based on the recently-proposed technique of shift switching with domino logic, where the charge/discharge signals propagate along the switch chain producing semaphores results in a network that is fast and highly hardware-compact. The proposed architecture for prefix counting

• Type: Conference
• Year: 1999
• Where: IPPS
• Authors: Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya
• Keywords: Chain Producing Semaphores, Distributed And Parallel Computing, IPPS 1999, Prefix Counting Network, Prefix Sum Units