Efficient worst case timing analysis of data caching

Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessary when a RISC processor is used as the target processor of a real-time system. However, there has not been much progress in worst case timing analysis of data caching. This is mainly due to load/store instructions that reference multiple memory locations such as those used to implement array and pointer-based references. These load/store instructions are called dynamic load/store instructions and most current analysis techniques take a very conservative approach to their timing analysis. In many cases, it is assumed that each of the references from a dynamic load/store instruction will miss in the cache and replace a cache block that would otherwise lead to a cache hit. This conservative approach results in severe overestimation of the worst case execution time (WCET). This paper proposes two techniques to m...

• Type: Conference
• Year: 1996
• Where: RTAS
• Authors: Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
• Keywords: Dynamic Load/store Instructions, Embedded Systems, Load/store Instructions, RTAS 1996, Timing Analysis