Enabling Partial Cache Line Prefetching Through Data Compression

Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buffers and causes significant memory traffic increase. In this paper we propose a new prefetching scheme which improves performance without increasing memory traffic or requiring prefetch buffers. We observe that a significant percentage of dynamically appearing values exhibit characteristics that enable their compression using a very simple compression scheme. The bandwidth freed by transferring values from lower levels in memory hierarchy to upper levels in compressed form is used to prefetch additional compressible values. These prefetched values are held in vacant space created in the data cache by storing values in compressed form. Thus, in comparison to other prefetching schemes, our scheme does not introduce prefetch buffers or increase the memory traffic. In comparison to a baseline cache that does ...

• Type: Conference
• Year: 2003
• Where: ICPP
• Authors: Youtao Zhang, Rajiv Gupta
• Keywords: Cache Miss, Distributed And Parallel Computing, ICPP 2003, Memory Traffic, Prefetch Buffers