Energy-aware error control coding for Flash memories

The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high density memory devices. However, cost of writing or programming Flash memories is an order of magnitude higher than traditional memories. In this paper, we design an algorithm to reduce both average write energy and latency in Flash memories. We achieve this by reducing the number of expensive `01' and `10' bit-patterns during error control coding. We show that the algorithm does not change the error correction capability and moreover improves endurance. Simulations results on representative bit-stream traces show that the use of the proposed algorithm saves, on average, 33% of write energy and 31% of latency of Intel MLC NOR Flash memory, and improves the endurance by 24%. Categories and Subject Descriptors B.3.2 [Memory Structures]: Mass storage; C.4 [Performance of Systems]: Fault tolerance General T...

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Veera Papirla, Chaitali Chakrabarti
• Keywords: DAC 2009, Design Automation, Error Correction Capability, Flash Memories, Keywords Flash Memories