Energy-optimized high performance FFT processor

This paper proposes an ultra low energy FFT processor suitable for sensor applications. The processor is based on R4MDC but achieves full utilization of computational elements. It has two parallel datapaths that increase throughput by a factor of 2 and also enable high memory utilization. The proposed design is implemented in 65nm CMOS technology and post-layout simulation including parasitic capacitances shows it achieves 9.25× higher energy efficiency than state-of-the-art FFT processors and high throughput relative to past subthreshold circuit implementations.

• Type: Journal
• Year: 2011
• Where: ICASSP
• Authors: Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester
• Keywords: Energy Fft Processor, Fft Processors, ICASSP 2011, Signal Processing, State-of-the-art Fft Processors