Evaluation of Neural and Genetic Algorithms for Synthesizing Parallel Storage Schemes

Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories whenever the data may be accessed in parallel allowed improvements in memory access time of 13% to 40%. We are concerned with dynamic storage schemes for which the compiler can predict some of the access patterns of parallelized programs. A storage scheme provides a mapping from array addresses into storages. However, finding a conflict-free storage scheme for a set of data patterns is NP-complete. This problem is reduceable to weighted graph coloring. Optimizing the address transformation is investigated by using: (1) constructive heuristics, (2) neural methods, and (3) genetic algorithms. The details of implementation of these different approaches are presented. Using realistic data patterns, simulation shows that memory utilization of 80% or higher can be achieved in the case of 20 data patterns over up to 256...

• Type: Conference
• Year: 2000
• Where: PDPTA
• Authors: Mayez A. Al-Mouhamed, Husam Abu-Haimed
• Keywords: Data Patterns, PDPTA 2000, PDPTA 2007, Problem Sizes, Storage Scheme