Event-driven gate-level simulation with GP-GPUs

Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ? to validate several aspects of the design, particularly functional correctness. Despite development houses investing vast resources in the simulation task, particularly at the gate-level, it is still far from achieving the performance demands required to validate complex modern designs. In this work, we propose the first event-driven logic simulator accelerated by a parallel, general purpose graphics processor (GPGPU). Our simulator leverages a gate-level event-driven design to exploit the benefits of the low switching activity that is typical of large hardware designs. We developed novel algorithms for circuit netlist partitioning and optimized for a highly-parallel GP-GPU host. Moreover, our flow is structured to extract the best simulation performance from the target hardware platform. We found that our e...

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
• Keywords: Commercial Event-driven Simulators, DAC 2009, Design Automation, Event-driven Logic Simulator, Gate-level Event-driven Design