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31

ICES
2007
Springer

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Evolving and Analysing "Useful" Redundant Logic

14 years 18 days ago

Evolving and Analysing "Useful" Redundant Logic

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Abstract. Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artiﬁcial evolution may be tuned to the creation of novel redundancy structures which may be applied to meet this challenge. An experimental setup and results for creating “useful” redundant structures is presented.

Asbjørn Djupdal, Pauline C. Haddow

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Fault Tolerance | Hardware | ICES 2007 | Integrated Circuits | Redundant Structures |

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Added	19 Oct 2010
Updated	19 Oct 2010
Type	Conference
Year	2007
Where	ICES
Authors	Asbjørn Djupdal, Pauline C. Haddow

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