Evolving and Analysing "Useful" Redundant Logic

Abstract. Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to the creation of novel redundancy structures which may be applied to meet this challenge. An experimental setup and results for creating “useful” redundant structures is presented.

• Type: Conference
• Year: 2007
• Where: ICES
• Authors: Asbjørn Djupdal, Pauline C. Haddow
• Keywords: Fault Tolerance, Hardware, ICES 2007, Integrated Circuits, Redundant Structures