Execution and Cache Performance of the Scheduled Dataflow Architecture

: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar and superspeculative architectures. This trend allows for better performance at theexpenseof anincreased hardware complexity and a brute-force solution to the memory-wall problem. Our research substantially deviates from this trend by exploring a simpler, yet powerful execution paradigm that is based on dataflow concepts. A program is partitioned into functional execution threads, which are perfectly suited for our non-blocking multithreaded architecture. Inaddition, all memory accessesare decoupled from the thread's execution. Data is pre-loaded into the thread'scontext (registers), and all results are post-stored after the completion of the thread's execution. The decoupling of memory accesses from thread execution requires a separate unit to perform the necessary pre-loads and poststores, an...

• Type: Journal
• Year: 2000
• Where: JUCS
• Authors: Krishna M. Kavi, Joseph Arul, Roberto Giorgi
• Keywords: Architectures, Better Performance, JUCS 2000, Processor Architectures