An experimental evaluation of tiling and shackling for memory hierarchy management

On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring compiler community has developed localityenhancing program transformations, the most well-known of which is loop tiling. Tiling is restricted to perfectly nested loops, but many imperfectly nested loops can be transformed into perfectly nested loops that can then be tiled. Recently, we proposed an alternative approach to locality enhancement called data shackling. Data shackling reasons about data traversals rather than iteration space traversals, and can be applied directly to imperfectly nested loops. We have implemented shackling in the SGI MIPSPro compiler which already has a sophisticated implementation of tiling. Our experiments on the SGI Octane workstation with dense numerical linear algebra programs show that shackled code obtains double the performance of tiled code for most of these programs, and o...

• Type: Conference
• Year: 1999
• Where: ICS
• Authors: Induprakas Kodukula, Keshav Pingali, Robert Cox, Dror E. Maydan
• Keywords: Distributed And Parallel Computing, ICS 1999, Memory Latency, Nested Loops, SGI MIPSPro Compiler