Experimenting with buffer sizes in routers

Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets. The underlying assumption is that the traffic is non-bursty, and that the system is operated below 85-90% utilization. In this paper, we present a test-bed for buffer sizing experiments using NetFPGA [2], a PCI-form factor board that contains reprogrammable FPGA elements, and four Gigabit Ethernet interfaces. We have designed and implemented a NetFPGA-based Ethernet switch with finely tunable buffer sizes, and an event capturing system to monitor buffer occupancies inside the switch. We show that reducing buffer sizes down to 20-50 packets does not necessarily degrade system performance. Categories and Subject Descriptors C.2.1 [Computer-Communication Networks]: Network Architecture and Design General Terms Experimentation, Performance

• Type: Conference
• Year: 2007
• Where: ANCS
• Authors: Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McKeown
• Keywords: ANCS 2007, Buffer Sizes, Buffer Sizing Research, Computer Networks, Tunable Buffer Sizes