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25

DFT
1997
IEEE

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Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments

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Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments

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Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo

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DFT 1997 | VLSI |

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Added	06 Aug 2010
Updated	06 Aug 2010
Type	Conference
Year	1997
Where	DFT
Authors	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar

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