This paper proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a Finite State Machine is modified to obtain a functionally equivalent circuit that exhibits a reduced power dissipation. The algorithm is based on a newly proposed power estimation function, that is able to quickly give an accurate estimate of the dissipated power without actually synthesizing the circuit. Given this estimate, a Genetic Algorithm provides a state re-encoding for the circuit. The estimation function is computed in a very efficient way by exploiting some symbolic computations with Binary Decision Diagrams. The algorithm is experimentally shown to provide good results from the power optimization point of view, at a limited cost in terms of area increase, when compared with similar approaches.
S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizi