Exploiting Vector Parallelism in Software Pipelined Loops

An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditional vectorization technology first developed for supercomputers. In contrast, scalar hardware is typically targeted using ILP techniques such as software pipelining. This paper presents a novel approach for exploiting vector parallelism in software pipelined loops. The proposed methodology (i) lowers the burden on the scalar resources by offloading computation to the vector functional units, (ii) explicitly manages communication of operands between scalar and vector instructions, (iii) naturally handles misaligned vector memory operations, and (iv) partially (or fully) inhibits the optimization when vectorization will decrease performance. Our approach results in better resource utilization and allows for software pipelining with shorter initiation intervals. The proposed optimization is applied in the compil...

• Type: Conference
• Year: 2005
• Where: MICRO
• Authors: Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe
• Keywords: Hardware, MICRO 2005, Software Pipelining, Traditional Vectorization, Vector Instructions