Fabrication of 3D Packaging TSV using DRIE

Emerging 3D chips stacking and MEMS/Sensors packaging technologies are using DRIE (Deep Reactive Ion Etching) to etch Through-Silicon Via (TSV) for advanced interconnections. The interconnection step can be done prior to or post wafer thinning, both requiring different etch process performances. A review of the DRIE capability in term of etching profile, etching rate, etching depth has been carried out. Excellent tool flexibility allows a wide range of basic and complex profiles to be achieved. Unlike other techniques, DRIE has the capability to etch feature sizes ranging from sub-micron to millimeter width. The main specificity of the DRIE is that the etching rate is sensitive to the total exposed area and the aspect ratio. For the TSV applications, where the total exposed area is lower than 10%, high etch rates are achievable. A study has also been carried out in order to highlight the importance of via profile for the success of the refilling step. Key words: TSV, Packaging, DRIE, ...

• Type: Journal
• Year: 2008
• Where: CORR
• Authors: M. Puech, Jean-Marc Thevenoud, J. M. Gruffat, N. Launay, N. Arnal, P. Godinat
• Keywords: CORR 2008, Deep Reactive Ion Etching, DRIE, Education, Etching