Faster projection based methods for circuit level verification

As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits using continuous models. Recently, we showed how such verification can be performed using projection based methods.However, the verification was slow, requiring nearly four CPU days to verify a nine-transistor toggle flip-flop. Here, we describe improvements to the reachability algorithms and optimizations of the software architecture. These produce a 15

• Type: Conference
• Year: 2008
• Where: ASPDAC
• Authors: Chao Yan, Mark R. Greenstreet
• Keywords: ASPDAC 2008, Hardware, Nine-transistor Toggle Flip-flop, Toggle Flip-flop, VLSI Fabrication Technology