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DSN
2004
IEEE

Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits

14 years 2 months ago
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits
This paper presents a novel circuit fault detection and isolation technique for quasi delay-insensitive asynchronous circuits. We achieve fault isolation by a combination of physical layout and circuit techniques. The asynchronous nature of quasi delay-insensitive circuits combined with layout techniques makes the design tolerant to delay faults. Circuit techniques are used to make sections of the design robust to non-delay faults. The combination of these is a asynchronous defecttolerant circuit where a large class of faults are tolerated, and the remaining faults can be both detected easily and isolated to a small region of the design.
Christopher LaFrieda, Rajit Manohar
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DSN
Authors Christopher LaFrieda, Rajit Manohar
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