Fault models for embedded-DRAM macros

In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively. Categories and Subject Descriptors B.8.1 [Hardware]: Reliability, Testing, and Fault-Tolerance General Terms Design Keywords Memory testing, embedded DRAM

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Ching-Yu Chin, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang, Shih-Chin Lin
• Keywords: DAC 2009, Design Automation, DRAM Testing, SRAM Test Algorithm, SRAM Testing