Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

80

ISCA
2009
IEEE

173views Hardware» more ISCA 2009»

A fault tolerant, area efficient architecture for Shor's factoring algorithm

15 years 9 months ago

A fault tolerant, area efficient architecture for Shor's factoring algorithm

Download isca09.cs.columbia.edu

Mark Whitney, Nemanja Isailovic, Yatish Patel, Joh

Real-time Traffic

Hardware | ISCA 2009 |

claim paper

Related Content

» Design and Implementation of Multiple Addresses Parallel Transmission Architecture for Sto...

» A Fuzzy Model for the Composition of Intrusion Detectors

» LUTbased FPGA technology mapping for reliability

» A scalable based multicast model for P2P Conferencing applications

» Lowcoordination topologies for redundancy in sensor networks

Post Info
More Details (n/a)

Added	24 May 2010
Updated	24 May 2010
Type	Conference
Year	2009
Where	ISCA
Authors	Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz

Comments (0)