Fine-grain performance scaling of soft vector processors

Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their prevalence and flexibility, soft processors are compelling targets for customization—although current soft processors provide few architectural variations. Recent work has proposed augmenting soft processors with customizable vector processing support, enabling designers to easily scale performance by exploiting the data parallelism available in an application. However this approach provides only coarsegrain scaling, by successively doubling the number of vector datapaths for less than double the performance. In this work we further augment soft vector processors with more fine-grain architectural modifications: we add support for (i) vector chaining and (ii) heterogeneous vector lanes, allowing the soft vector processor to be customized to not only the data-level parallelism available in an application...

• Type: Conference
• Year: 2009
• Where: CASES
• Authors: Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
• Keywords: Augment Soft Vector, CASES 2009, Communications, Soft Processors, Soft Vector Processors