The Formal Simulation Semantics of SystemVerilog

We present a rigorous but transparent semantics definition of SystemVerilog that covers processes with blocking and non-blocking statements as well as their interaction with the simulation scheduler including the management of new SystemVerilog regions. We present our definition in form of ted Abstract State Machines (ASMs) rules reflecting the view given in the SystemVerilog Language Reference Manual [1]. Our formal semantics is a concise, unambiguous, high-level specification for SystemVerilog-based implementations and for investigation of interoperabilities of SystemVerilog with SpecC, SystemC, and VHDL.

• Type: Conference
• Year: 2004
• Where: FDL
• Authors: Martin Zambaldi, Wolfgang Ecker, T. Kruse, W. Müller
• Keywords: FDL 2004, Natural Language Processing, SystemVerilog, SystemVerilog Language Reference, Transparent Semantics Definition