A FPGA architecture for real-time processing of variable-length FFTS

A new FFT architecture for real-time implementation of large FFTs is presented. The architecture supports both, highthroughput and variable-length processing capabilities. The implementation is con gurable at run-time, in order to compute power-of-two length ranging from 16 to 2n . It supports ef cient integration of data scaling techniques. A radix-23 DIT FFT algorithm is derived, which minimizes the number of multipliers and supports simple reordering.

• Type: Journal
• Year: 2011
• Where: ICASSP
• Authors: Stefan Langemeyer, Peter Pirsch, Holger Blume
• Keywords: DIT FFT Algorithm, Ef Cient Integration, ICASSP 2011, Signal Processing, Variable-length Processing Capabilities