FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards

In 1996, about 600 million IC-cards were manufactured worldwide. Due to very small die sizes (max. 25 mm2 ) smartcards encounter more severe restrictions than conventional coprocessors. In this paper we study coprocessor architectures for very fast but area efficient modular exponentiation (FME) based on Montgomery multiplication. For assessment purposes we developed an evaluation board containing a 8051-microprocessor, a XILINX FPGA and RAM with variable bus width (8b to 32b). We evaluated these architectures in terms of the main design parameters to ease design decisions for smartcards in arbitrary technologies.

• Type: Conference
• Year: 1998
• Where: FCCM
• Authors: Hagen Ploog, Dirk Timmermann
• Keywords: Coprocessor Architectures, Efficient Modular Exponentiation, FCCM 1998, Variable Bus Width, VLSI