An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic

An improved FPGA implementation of an electronic cochlea filter is presented. We show that by using decimation, the computations of the electronic cochlea can be reduced. Furthermore, employing dual fixed-point arithmetic, gives a significant improvement in signal to noise ratio. A sequential architecture is described which employs pipelined infinite impulse response filter stages. The accuracy, performance and resource utilisation of a number of different implementations are compared.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: C. K. Wong, Philip Heng Wai Leong
• Keywords: Electronic Cochlea, Electronic Cochlea Filter, FPL 2006, Hardware, Improved Fpga Implementation