FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators

Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can customize the hardware by selecting from a large number of pre-defined peripherals and fixed IP functions and by providing new hardware, typically expressed using RTL. Hardware accelerators that provide application-specific extensions to the computational capabilities of a system is an efficient mechanism to enhance the performance and reduce the power dissipation. What is missing is an integrated approach to identify the computationally critical parts of the application and to create accelerators starting from a high level representation with a minimal design effort. In this paper, we present an automation methodology and a tool that generates accelerators. We apply the methodology on an FPGA-based license plate recognition (LPR) system used in law enforcement. The accelerators process streaming data and support...

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier
• Keywords: Distributed And Parallel Computing, Hardware, Hardware Accelerators, IPPS 2006, Large Number