FPGA Implementations of the ICEBERG Block Cipher

— This paper presents FPGA (Field Programmable Gate Array) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and Encrypt/Decrypt (E/D) mode for every plaintext, without any performance loss. In comparison with other recent block ciphers, the implementation results of ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and E/D agility allows considering new encryption modes to counteract certain side-channel attacks.

• Type: Conference
• Year: 2005
• Where: ITCC
• Authors: François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater
• Keywords: Block Ciphers, Field Programmable Gate Array, Information Technology, ITCC 2005, Reconfigurable Hardware Implementations