FPGA Implementations of the ICEBERG Block Cipher

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— This paper presents FPGA (Field Programmable Gate Array) implementations of ICEBERG, a block cipher designed for reconﬁgurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efﬁcient combinations of encryption/decryption. The implementations proposed also allow changing the key and Encrypt/Decrypt (E/D) mode for every plaintext, without any performance loss. In comparison with other recent block ciphers, the implementation results of ICEBERG show a signiﬁcant improvement of hardware efﬁciency. Moreover, the key and E/D agility allows considering new encryption modes to counteract certain side-channel attacks.

François-Xavier Standaert, Gilles Piret, Ga

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Block Ciphers | Field Programmable Gate Array | Information Technology | ITCC 2005 | Reconﬁgurable Hardware Implementations |

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Added	25 Jun 2010
Updated	25 Jun 2010
Type	Conference
Year	2005
Where	ITCC
Authors	François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater

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FPGA Implementations of the ICEBERG Block Cipher

Block Ciphers | Field Programmable Gate Array | Information Technology | ITCC 2005 | Reconﬁgurable Hardware Implementations |

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