FPGA Performance Optimization Via Chipwise Placement Considering Process Variations

Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom to leverage process variation and improve circuit performance. We propose the following variation aware chipwise placement flow in this paper. First, we obtain the variation map for each chip by synthesizing the test circuits for each chip as a preprocessing step before detailed placement. Then we use the trace-based method to estimate the performance gain achievable by chipwise placement. Such estimation provides a lower bound of the performance gain without detailed placement. Finally, if the gain is significant, a variation aware chipwise placement is used to place the circuits according to the variation map for each chip. Our experimental results show that, compared to the existing FPGA placement, variation aware chipwise placement improves circuit performance by up to 19.3% for the tested variation maps.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
• Keywords: Aware Chipwise Placement, FPL 2006, Hardware, Variation Aware Chipwise, Variation Maps