Full Custom VLSI Implementation of High-Speed 2-D DCT/IDCT Chip

In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. We show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. Our design of the 8 x 8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1 . 2 ~CMOS technology.

• Type: Conference
• Year: 1994
• Where: ICIP
• Authors: Vishnu Srinivasan, K. J. Ray Liu
• Keywords: Conservative Estimate, Full-custom Vlsi Design, ICIP 1994, Image Processing, VLSI Implementation